桶形移位寄存器工作原理_移位寄存器verilog-

桶形移位寄存器工作原理_移位寄存器verilogFPGA综合过程要在速度与面积之间进行折中考虑。“资源共享”是面积的优化技术。在设计中牺牲一些硅片的面积，往往会增加速度.以下代码使用了两级复用器，其速度得到提高。复用器共3级个4选一复用器。对第一级，对输入数据进行0，1，2或3位循环移位；第二级，对输入进行0，4，8，12位的循环移位，第三级，对输入进行0，16，20，20位的循环移位。—————————

FPGA综合过程要在速度与面积之间进行折中考虑。“资源共享”是面积的优化技术。在设计中牺牲一些硅片的面积，往往会增加速度.以下代码使用了两级复用器，其速度得到提高。复用器共3级个4选一复用器。对第一级，对输入数据进行0，1，2或3位循环移位；第二级，对输入进行0，4，8，12位的循环移位，第三级，对输入进行0，16，20，20位的循环移位。

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

—- Uncomment the following library declaration if instantiating

—- any Xilinx primitives in this code.

–library UNISIM;

–use UNISIM.VComponents.all;

entity A_reg_changer is

Port ( clk : in STD_LOGIC;


rst: in std_logic;

A_reg : in STD_LOGIC_vector(31 downto 0);

B_reg : in STD_LOGIC_vector(5 downto 0);


reg_32_B : in std_logic_vector(5 downto 0);


B_reg_d1 : out std_logic_vector(5 downto 0);

A_reg_change : out STD_LOGIC_vector(63 downto 0)


);

end A_reg_changer;

architecture Behavioral of A_reg_changer is

signal SEC1,SEC2,SEC3: std_logic_vector(1 downto 0);

signal A_reg1,A_reg2,A_reg3: std_logic_vector(31 downto 0);

begin

output:process(rst,clk)

begin

if rst =’1′ then

B_reg_d1 <=(others=>’0′);


A_reg_change<=(others=>’0′);

else


if clk’event and clk=’1′ then


B_reg_d1 <= B_reg;


A_reg_change(31 downto 0)<= (others=>’0′);


A_reg_change(63 downto 32)<= A_reg3;


end if;


end if;

end process;

————– 63bit_barrel_shifter for making the A_reg into the form like this:

————–(the available value of register A | all ‘0’)

———-level 1————–

bs_lv1:process(SEC1,A_reg) –“bs” shorts for barrel-shifter

begin

case SEC1 is

when “00” => –shift 0

A_reg1<=A_reg;

when “01” => –shift 1

A_reg1(0)<=’0′;

A_reg1(31 downto 1)<=A_reg(30 downto 0);

when “10” => –shift 2

A_reg1(1 downto 0)<=(others=>’0′);

A_reg1(31 downto 2)<=A_reg(29 downto 0);

when “11” => –shift 3

A_reg1(2 downto 0)<=(others=>’0′);

A_reg1(31 downto 3)<=A_reg(28 downto 0);

when others=>

A_reg1<=A_reg;

end case;

end process;

———-level 2————–

bs_lv2:process(A_reg1,SEC2)

begin

case SEC2 is

when “00”=>

A_reg2<=A_reg1;

when “01”
=> –shift 4

A_reg2(3 downto 0)<=(others=>’0′);

A_reg2(31 downto 4)<=A_reg1(27 downto 0);

when “10” => –shift 8

A_reg2(7 downto 0)<=(others=>’0′);

A_reg2(31 downto 8)<=A_reg1(23 downto 0);

when “11” => — shift 12

A_reg2(11 downto 0)<=(others=>’0′);

A_reg2(31 downto 12)<=A_reg1(19 downto 0);

when others=>

A_reg2<=A_reg1;

end case;

end process;

———-level 3————–

bs_lv3:process(A_reg2,SEC3)

begin

case SEC3 is

when “00” =>

A_reg3 <= A_reg2;



when “01” => –shifter 16

A_reg3(15 downto 0)<=(others=>’0′);

A_reg3(31 downto 16)<=A_reg2(15 downto 0);


when “10”=> –shifter 32

A_reg3<= (others=>’0′);

when others =>

A_reg3<= A_reg2;

end case;

end process;

SEC1<=reg_32_B(1 downto 0);

SEC2<=reg_32_B(3 downto 2);

SEC3<=reg_32_B(5 downto 4);

end Behavioral;