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10分频电路(非

分频器)

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY clk_p ISPORT(clkin:IN STD_LOGIC;clkout:OUT STD_LOGIC);END clk_p;ARCHITECTURE clk_p_behavior OF clk_p ISSIGNAL counter:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL temp:STD_LOGIC;BEGINPROCESS(clkin)BEGINIF(clkin'EVENT AND clkin='1')THENIF(counter="100")THEN        --注意,这里是0——4,一个周期1:1的高低电平counter<="000";temp<=NOT temp;ELSEcounter<=counter+1;ENDIF;END IF;END PROCESS;clkout<=temp;END clk_p_behavior;

分频电路(2,4,8分频电路)

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY clk_p ISPORT(clk:IN STD_LOGIC;clk_p_2:OUT STD_LOGIC;clk_p_4:OUT STD_LOGIC;clk_p_8:OUT STD_LOGIC);END clk_p;ARCHITECTURE clk_p_behavior OF clk_p ISSIGNAL counter:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINPROCESS(clk)BEGINIF(clk'EVENT AND clk='1')THENIF(counter="111")THENcounter="000";ELSEcounter<=counter+1;END IF;END IF;END PROCESS;clk_p_2<=NOT counter(0);clk_p_4<=NOT counter(1);clk_p_8<=NOT counter(2);END clk_p_behavior;

占空比为2:4的6分频器

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY clk_p ISPORT(clk:IN STD_LOGIC;clk_p_6:OUT STD_LOGIC);ENDclk_p;ARCHITECTURE clk_p_bahavior OF clk_p ISSIGNAL temp:STD_LOGIC_VECTOR(2 DOWNTO 0);CONSTANT counter:STD_LOGIC_VECTOR(2 DOWNTO 0):="101";BEGINPROCESS(clk)BEGINIF(clk'EVENT AND clk='1')THENIF(temp=counter)THEN--控制分频temp<="000";ELSEtemp<=temp+1;END IF;END IF;END PROCESS;PROCESS(clk)BEGINIF(clk'EVENT AND clk='1')THENIF(temp="001")--控制占空比clk_p_6<='1';ELSEclk_p_6<='0';END IF;END IF;END PROCESS;END clk_p_bahavior;

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